Analog integrated circuits (ICs) are integrated circuits that process analog signals. Examples of such circuits include, for example, amplifiers, reference current sources, and reference voltage sources. Analog ICs often require the use of, and constantly consume, a DC bias current. Digital integrated circuits are ICs which process digital signals. Examples of digital integrated circuits include, for example, logical circuit and state machines, such as processors. Digital circuits with complementary metal oxide semiconductor (CMOS) logic generally do not use a DC bias current.
Some integrated circuits, however, process both analog and digital signals. Such circuits are known as mixed signal integrated circuits. Mixed signal ICs generally require the use of a DC bias current supply. A common example of a mixed signal circuit is an analog-to-digital converter (ADC). ADCs accept an input analog signal and produce an output digital signal having a value corresponding to the magnitude of the input analog signal. ADCs are found in numerous products, including a variety of portable electronic devices, such as CMOS based imaging products. Many CMOS based imaging products include ICs that include a plurality of ADCs, so that a plurality of analog signals can be simultaneously converted to corresponding digital signals. Since portable electronic devices are generally battery powered, it is desirable to reduce the power consumption of mixed signal ICs, such as those ICs which include ADCs.
FIG. 1 illustrates general features of a conventional pipelined ADC 100. ADC 100 comprises a clock generator 110, a reference voltage source 120, a plurality of cascaded identical stages 101, and a digital block 130. The digital block 130 provides N output bits, one for each of stages 101.
Now also referring to FIG. 3, it can be seen that the clock generator 110 accepts a clock signal φand produces two non-overlapping clock signals φ1 and φ2. The two clock signals φ1 and φ2 are generated so that they define distinct phases for each clock cycle of the original clock signal φ. In each stage 101 of a typical ADC 100, different tasks are performed during the different phases defined by clock signals φ1 and φ2. For example, in each odd stage 101 (e.g., a first, third, fifth, etc. stage of the ADC 100), when clock signal φ1 is high, the stage 101 is in a sampling phase, and when clock signal φ2 is high, the stage 101 is in a conversion phase. Each adjacent phase utilizes the clock signals φ1 and φ2 in a complementary fashion. Thus, in the above example, each even stage 101 (e.g., a second, fourth, sixth, etc. stage 101 of the ADC 100) is in a conversion phase when clock signal φ1 is high and each even stage is in a sampling phase when clock signal φ2 is high. The reference voltage generator 120 accepts a power signal from the power supply (not illustrated) and outputs a reference voltage signal Vref. The two clock signals φ1, φ2 and the reference voltage signal are supplied to each stage 101.
Each stage 101 accepts an input signal and outputs an output signal. The stages 101 are cascaded, so that the first stage 101 accepts an input signal at terminal 150 and outputs a signal which becomes the input signal for the next stage; and so forth. More specifically, when clock signals φ1 or φ2 corresponds to a sampling phase of a given stage 101 of the ADC 100, the input signal of each stage 101 is distributed to processing block 103 and a first input terminal for amplifier block 102.
Processing block 103 implements the well known process of performing an analog-to-digital conversion of the input signal and generating an analog signal corresponding to the (partially) converted digital signal. The generated analog signal, when presented as an input signal to amplifier 215 of the amplifier block 102, generates a residual analog signal in the amplifier 215 which, after amplification, would be suitable for use in the next stage of the pipeline. More specifically, in processing block 103, the input signal is converted into a 2-bit digital signal B0, B1. The 2-bit digital signal B0, B1 is output to the digital block 130. Additionally, the 2-bit digital signal B0, B1 is used to control a digital-to-analog converter (in processing block 103), which supplies an analog signal corresponding to the converted value to a second input terminal of the amplifier block 102. Since the amplifier block 102 accepts a differential input signal in which the magnitude of the input signal is the voltage difference between the two inputs, the amplifier block receives at its inputs what is known in the art as the residual signal (i.e., the original signal minus the converted value).
FIGS. 2A and 2B are block diagrams of the amplifier block 102, which illustrate the amplifier block 102 as comprising a switched capacitor amplifier 210 (FIG. 2A) and a common mode feedback circuit 250 (FIG. 2B). The switched capacitor amplifier 210 is a network comprising a pair of input terminals 211a, 211b, respectively for a differential input signal comprising signals Vinp (coupled to the Vin signal) and Vinn (coupled to the output signal from processing block 103); a pair of input terminals 211c, 211d respectively for a differential reference signal comprising signals Vrefp, Vrefn; input terminal 211e for a common mode voltage reference signal Vcm (in the middle of the power supply range); switches 212a and 212b respectively controlled by clock signals φ1 and φ2; capacitors 213a, 213b, 214a, 214b; nodes A, B, and C; amplifier 215; and output terminals 216a and 216b, respectively for a differential output signal comprising signals Voutn and Voutp, arranged as shown. Switches 212a are closed when clock signal φ1 is high and open when clock signal φ1 is low. Similarly, switches 212b are closed when clock signal φ2 is high and open when clock signal φ2 is low. The relationship between clock signals φ1 (high during a sampling phase of the ADC) and φ2 (high during a conversion phase of the ADC) is shown in FIG. 3. Typically, capacitors 213a and 213b are identical, and 214a and 214b are also identical.
The common mode feedback circuit 250 includes input terminal 251 for receiving the common mode voltage Vcm; input terminal 216 for receiving a bias voltage Vbias; switches 252a and 252b which are respectively controlled by clock signals φ1 and φ2; capacitors 253-256; and nodes A, B, and C, respectively coupled to corresponding nodes of the switched capacitor amplifier 210. Switches 252a are closed when clock signal φ1 is high and open when clock signal φ1 is low. Similarly, switches 252b are closed when clock signal φ2 is high and open when clock signal φ2 is low.
The processing performed in the processing block 103 is primarily digital processing and little power is wasted there. However, the processing performed in the amplifier block is analog processing, and as described below, wasteful in power consumption.
While clock φ1 is high, in addition to the above-described processing performed by the processing section 103, the differential input signals at the amplifier block 102, i.e., signals Vinp and Vinn, are respectively sampled by input capacitors 213a, 213b. Additionally, a common mode voltage Vcm is supplied to the opposite side of each capacitor. The common mode voltage Vcm is typically set to the average value between the voltage levels of the two power supply rails. That is, if one power supply rail is ground and another is 5 volts, Vcm would be 2.5 volts. During this phase, the amplifier 215 is idle, and the outputs Voutn, Voutp of the amplifier 215 are shorted to each other. Outputs Voutn, Voutp are each maintained at a voltage level equal to the common mode voltage Vcm via the common mode feedback circuit 250. Once adequate time has elapsed to permit capacitors 213a, 213b, 214a, 214b to sample the input signals Vinp, Vinn, the clock signal φ1 goes low and the sampling phase ends.
At the same time, clock signal φ2 goes high, to indicate the start of the conversion phase. During this phase, no processing is performed by the processing section 103. However, in amplifier block 102, capacitors 213a, 213b are coupled as inputs to the amplifier 215 and capacitors 214a, 214b, are connected to provide negative feedback across amplifier 215. The amplifier 215 produces an output signal comprising signals Voutn, Voutp in accordance with equation (1) below:(Voutp−Voutn)/(Vinp−Vinn)=(1+(Cin/Cfb))  (1) , where Cin is the capacitance of a input capacitor, such as capacitor 213a, and Cfb is the capacitance of a feedback capacitor, such as capacitor 214a. Since each stage of the ADC 100 is responsible for ultimately converting 1-bit of the entire analog-to-digital processing, a gain of 2.0 is desired (since each bit differs in magnitude from the next bit by a factor of 2). Typically, this is achieved by setting Cin equal to Cfb.
One problem associated with the above described operation is that each stage 101 of the analog to digital converter 100 is operated in a manner which wastes power. More specifically, in each stage 101, the amplifier 215 is idle during the sampling phase but still consumes bias current. Additionally, during the sampling phase, the outputs of the amplifier 215 are shorted together. As a result, during the conversion phase, the outputs of the amplifier must slew from the common mode voltage (Vcm) to the appropriate voltage. This slewing between the common mode and required voltage further increases power consumption and affects accuracy of settling time.
Accordingly, it would be advantageous to increase power efficiency and improve operation an analog to digital converter.